Such driver circuits are used in low power digital circuits, in particular integrated circuits, to interface to higher power circuitry, or via interconnections to circuitry on another circuit board, another integrated circuit chip, or even within the same chip. The effective load is therefore typically characterized by a load circuit impedance ZL in parallel with a large capacitance CL of the interconnections, as illustrated at the output of a conventional driver circuit in FIG. 1. The circuit of FIG. 1 may be constructed for example in complementary MOS (CMOS) technology. Two inverters 10 and 12 in cascade form the driver circuit, receiving an input signal VI on an input line 18 and generating a corresponding output signal VO across the load on an output line 20.
FIG. 2, curve (a) shows a high-to-low transition in the input signal VI while FIG. 2, curve (b) shows the output transition in VO which results after a few nanoseconds propagation delay. In order that the output transition may occur at high speed, the inverter 12 is constructed using large transistors to give the circuit a low output impedance so that it may discharge the capacitance CL rapidly by conducting a large output current 10. Unfortunately, the line capacitance CL and inductances L1-L3 in the output line 20 and the supply lines 14 (VCC) and 16 (GND) respectively form a resonant circuit, and the low output impedance enables the output signal VO to overshoot the desired low level (GND) and to continue "ringing" (oscillating around the desired level) for several cycles. This ringing is a noise source which can lead to spurious transitions being detected by the load circuit and by nearby circuits connected to the same supply lines. Consequently, the designer of a conventional driver circuit is forced to accept a compromise between switching speed and switching noise.
In FIG. 3, curve (a) illustrates the ground supply current IGND drawn by the inverter 12 from the supply line 16 (GND) during the transition. In addition to a large peak of supply current (at F), reflecting the large output current required to discharge the load capacitance, the ringing is reflected in a series of peaks in the current IGND, which represent a considerable waste of power (generating heat), as well as being a source of noise. FIG. 3, curve (b) shows the supply current IVCC drawn from the positive supply VCC. This current IVCC is not large during the high-to-low output transition illustrated, but in the case of the complementary (low-to-high) transition, the roles of IVCC and IGND will be substantially reversed.
The problem of switching noise in outputs and supply lines is a general one, but is particularly acute in circuit technolgies such as CMOS, where the output driving is provided by insulated gate field effect transistors (including, for example, MOS transistors). Such devices when turned on act very much like simple resistors, lacking the rectifying properties of bipolar transistors.